1. Field of the Invention
The present invention relates to a structure and method for stopping internal clocks of an integrated circuit to facilitate IN-testing of the integrated circuit.
2. Description of Related Art
The market for semiconductor devices is becoming increasingly competitive as more manufacturers are introducing a wider variety of semiconductor products. With many products from which to choose, consumers are able to make greater performance demands. Recognizing the significance that an integrated circuit's performance may play in the marketplace, manufacturers employ various tests to ensure that each of their respective integrated circuits (ICs) performs as intended.
One well known method of testing the performance of a particular IC is to subject the IC to what the semiconductor industry has termed an "IN-Test." To perform such a test, scannable elements within the logic of the IC are connected in a signal path to one another to form a scan chain. With the IC in a scan mode, a test vector is provided as an input signal to the IC. After allowing the IC to operate for a number of clock cycles, the internal clocks of the IC are stopped, thereby disabling the IC system logic so as to "freeze" the logic states within the scannable elements. The IC is then clocked with a separate scan clock so as to capture, or "scan" out, these logic states as an output vector. The output vector is read from an output port of the IC and compared to a reference vector to determine if the IC has operated correctly.
In performing such an IN-Test, the internal clocks are typically stopped by stopping the external oscillator that generates the internal clocks. Stopping the external oscillator in such a manner is not only inconvenient but also may result in harmful jitters.
Thus, it would be desirable to perform an IN-Test without stopping the external oscillator that provides the internal clocks to the IC.